Multiplexing arrangement used in converting an ac signal to a dc signal

ABSTRACT

A method of converting an AC voltage to a DC voltage corresponding substantially to the fundamental sinusoidal AC components by dropping said AC voltage through an input line across a series resistor and parallel capacitor, to an output line, comprising the step of opening up the input line at a predetermined time of the changing input sinusoidal voltage depending on its frequency and the values of the capacitor and resistor so as to obtain a DC voltage having a large percentage of the AC sinusoidal fundamental component while minimizing the effects of the harmonic and quadrature content.

Inventors Appl. No.

Filed Patented Assignee nited States Patent MULTIPLEXING ARRANGEMENTUSED IN CONVERTING AN AC SIGNAL TO A DC SIGNAL 3 Claims, 7 Drawing Figs.

us. (I 328/139, 328/151, 328/166 Int. Cl n03!) 1/04 Field of Search328/26, 28,

[56] References Cited UNITED STATES PATENTS 3,041,479 6/1962 Sikorra328/166 UX 3,119,984 1/1964 Brandt et al. 328/151 X 3,223,848 12/1965Molnar et al. 328/166 X Primary Examiner-John Zazworsky Att0meysS. A.Giarratana and S. Michael Bender ABSTRACT: A method of convening an ACvoltage to a DC voltage corresponding substantially to the fundamentalsinusoidal AC components by dropping said AC voltage through an inputline across a series resistor and parallel capacitor, to an output line,comprising the step of opening up the input line at a predetermined timeof the changing input sinusoidal voltage depending on its frequency andthe values of the capacitor and resistor so as to obtain a DC voltagehaving a large percentage of the AC sinusoidal fundamental componentwhile minimizing the effects of the harmonic and quadrature content.

SYNCHRO TO DIGITAL CONVERTER DIGITAL COMPUTER PATENTED UEE28 1971 SHEET1 BF 3 FlCiZc:

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(JORC 2 tofu- L l Pic-3.26

INVL'}, 1 4 5 HERBERTS.JARECK| BOB N. NAYDAN ATTORNEY TO s AND s TO SI+s|| PHASE SHIFT NETWORK CR ll PATENTEDIDEQB IEIII FROM EXTERNAL ADDRESSCONTROLS lNV[;l"-"/ORS HERBERTSJARECK/ BOB N NAYDAN IO I6 (4| A ACREFERENCE ZERO CROSSING DETECTOR TIMING INTERVAL w INPUT REFERENCEMULTIPLEXING ARRANGEMENT USED IN CONVERTING AN AC SIGNAL TO A DC SIGNALThis application is a continuation-in-part of application Ser. No.641,347, filed May 25, I967, now abandoned and commonly assigned.

BRIEF SUMMARY OF THE INVENTION The present invention relates to theconversion of an AC input into a corresponding DC signal which can beused in an analog to digital converter.

In various instruments, the external input, e.g., velocity is measuredby AC instruments. To convert the AC output into digital form, the ACmust often be converted into DC.

Heretofore, the AC to DC conversion was often obtained by eitherinstantaneous sampling the peak of the AC signal or taking the RMS ACvalue. However, an AC signal is an extremely complex thing. The signalis depicted schematically as a sinusoidal wave shape. This theoreticalwave is not what is produced in reality. On the contrary, the wave shapeproduced contains the basic signal as well as quadrature voltage factorsand harmonic voltages. By merely sampling the RMS or peak value of thewave, the quadrature and harmonic rejection obtainable is too low formany accurate system requirements.

According to the present inventive concept, the input AC is passedthrough an RC integrator structure having certain predetermined values,together with a switching arrangement. The circuit values and gau'ngtimes are arranged to produce the desired combinations of optimum outputsignal, quadrature and harmonic rejection.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING FIG. 1 is a partlyschematic partly block diagram explanation of the inventive concept;

FIG. 2a represents schematically some of the equivalent circuitry ofFIG. I;

FIG. 2b is a mathematical explanation of some of the expressions givenin the specification;

FIG. 2c is a similar mathematical expression of some of the expressionsgiven in the specification;

FIG. 3 is a schematic diagram of one embodiment of the invention;

FIG. 4 is a schematic circuit diagram showing a portion of theembodiment of FIG. 3 in more detail; and

FIG. 5 is a timing diagram showing the relationship among the varioussignal waveforms produced within the circuit of FIG. 4.

BRIEF DESCRIPTION OF INVENTION Turning now to FIG. 1, there is shown arepresentative circuit embodying the principals of the present inventionand including a plurality of input lines controllably energized by alike plurality of switches S,, S MS Each input line, when its respectiveswitch is in a closed condition, is adapted to apply an AC sinusoidalvoltage E,, E,,,...E- across an RC network comprising a series resistorR, and a capacitor C, connected in parallel between resistor R, andground. The output of this RC network is directly coupled to anamplifier A which functions merely as a buffer reproducing at its outputexactly that which appears at its input. The circuit of FIG. 1, includesfinally, a switch 8,, coupled in parallel between the output of the RCnetwork and ground for selectively discharging the voltage stored oncapacitor C, when the switch is actuated to a closed condition.

Signals E, through E, respectively include a fundamental frequencycomponent, harmonics thereof, as well as quadrature components. Thus, inthe operation of the circuit of FIG. I, assume that switches S through8,, and 8,, are all open circuited and that S, is closed or shortcircuited. The input voltage E, then will consist of a fundamentalfrequency component A, sin an, odd harmonic frequency components and aquadrature component B, cost on.

Using LaPlace transformation techniques, the output signal E, may beexpressed as:

(harmonics term) B,(wR1C1 sin wt+cos wtw en quadrature term) 7 Thederivation of the foregoing equation is obtained from FIGS. 2a, 2b, and2c and LaPlace transfer function tables as follows. Considering thecircuit of FIG. 1 from the standpoint of the equivalent circuit shown inFIG. 2a, the transfer function of an RC network is:

e (sine wave) The LaPlace transform will be m T 1/T(1/T +w) =-sin(teak-tan" wT) [sin wt cos [tanwT] cos wt sin [tan wT] From Figure 2b,the following are the trigonometric relationships wi d-( sin [tanwT]= 1cos [tan wT] arms I Therefore,

Therefore,

Dividing by wT,

EmwT 1 (e- -l- -cos wt) Resubstituting T=RC EmwRC sin wt To obtain termsfor quadrature input, the cosine input 25 is applied as follows:

The expression for a cosine wave is: 3

s v I/RC "(s' +w )(8+ 1 120 From the aforementioned book of Gardner andBarnes Equation 1.210,

=sin wt cos +wt sin 5 -1 -1 sin t cos (tan R +cos wt sin (tan and fromFigure 2c sin (wt-l-dz) Equation (3) may now be expanded and reexpressedin the form of equation l In accordance with the present invention, thepurpose of using the circuit configuration of FIG. 1 is to obtain anoutput DC voltage E, that is proportional to the input fundamental ACvoltage. Moreover, since the harmonic and quadrature components of theinput signal contain no useful information, it is desirable to reducethe effects of these components on the output voltage as much aspossible. This is accomplished according to the present invention in thefollowing prescribed manner. Noting from equation l that the outputlevel E, will vary for different values of wRC and out, equation l issolved over a given range of such values by setting the quadrature termin the equation equal to zero. That is, for each preselected value ofwRC, wt, and zero quadrature component equation (1) may be solved toyield corresponding values of output voltage E,, which latter includescontribution from both the input fundamental component and the inputharmonic components. The results of such a computation forrepresentative values of wRC and wt where A A(2N-1 and B, have beennormalized to i are reproduced in the five leftmost columns of thefollowing table:

TABLE E a d LE0 9 t due to hardB 2 Quad. fund monlc wRC wt comp. comD.comv- RIC! 1.6"- it j 1r 0 m3 .019 .485

From this table it will be observed that for certain optimum values ofwRC and cut, the output signal E will comprise a voltage termsubstantially proportional to the input fundamental with almost completeattentuation of the first odd harmonic, i.e., the third harmonic, andwith of course, complete rejection of the quadrature component. Toillustrate by way of example, assume that a sinusoidal AC input signalE, of known frequency is impressed across the RC network of FIG. 1wherein from the above table wRC is chosen to be equal to 1.6. Supposenow that at a time T, corresponding to the beginning of a cycle of theinput waveform switch S, is short circuited and switch 8,, is openedthereby causing capacitor C, to charge up. From the table, thecorresponding value for (at is equal to (141/1 80)1r radians which meansthat if the switch S, is then opened at a later time T, corresponding tol4l of angular displacement of the input wavefonn, the voltage appearingacross capacitor C, (i.e., at the output of the RC network and thereforethe output of amplifier A,-) will comprise a voltage E having noquadrature component, a component equal to 0.623 of the inputfundamental and a component equal to only 0.019 of the input thirdharmonic. It is apparent therefore that the voltage held on capacitor C,at the end of the time interval T -T, will comprise a DC voltagesubstantially proportional to the input AC fundamental. Switch 8,, maythen be short-circuited thereby discharging capacitor C, to ground andresetting the circuit in preparation for the next input cycle which, ofcourse, may be that associated with, say, the input signal E beingapplied to the RC network of FIG. 1 through switch 8;. Input signal B,will thus be held across capacitor C, for the time interval T -T, in amanner exactly identical to that described above with the remainingchannels E -E being processed in similar fashion.

The question may arise as to what effect changes in R,C, due to aging ofthe components, temperature changes, and the like have on the outputvoltage E,,. By partially differentiating equation (I) an expression maybe derived representing the percentage change in E, with respect to apercentage change in R, C,. Thus:

By substituting the corresponding values of wRC and wt into thisequation the sensitivity factors for such values may be given. Thesevalues are reproduced in the rightmost column of the table. Thus, in theillustrated example where wRC is equal to L6, the correspondingsensitivity factor is equal to 0.485 which indicates that for every unitchange in R,C, the charge in E, is only about half as much. Thus it maybe concluded that the circuit of FIG. 1 is virtually insensitive tochanges in RC and this constitutes one of the important advantages ofthe present invention. ln carrying out the principles of the presentinvention a described hereinabove with reference to FIG. 1, it isimportant that switches 8, through 8,, and 8,, be properly actuated inthe preferred sequence so as to apply the input AC signal from eachselected channel across the RC network for the interval of time T,,-T,,it being recalled that T, represents the beginning of a cycle of theinput fundamental waveform. A sequence or timing means for accomplishingthis purpose will now be described in connection with FIGS. 3 through 5.Turning now to FIG. 3, there is shown an AC to DC converter inaccordance with the present invention, which congerter may be used inconnection with an analog-todigital converter such as that described inthe George F. Schroeder et al. US Pat. No. 3,071,324. The arrangementshown in FIG. 3 depicts four inputs, sin A, cos A; sin B, cos B; sin C,cos C; sin D, cos D. These inputs are applied to the type of circuitarrangement shown in FIG. 1. In the case of FIG. 3, there are both asine and a cosine channel so that in addition to switches S, through 8,for the sine channel there is also a cosine channel having switches 8,,through S to which the cosine inputs cos A through cos D are applied.Each input is applied across a separate line with a separate resistor;namely, R, for sin A, R for sin B, etc. and R,,,, for cos A, R for cosB, etc. The various switches S, through S and 8,, through 8,, areoperated by a timer T. Only one channel at a time is connected to theinput to the AC to DC converter junction points J and J The particularinput passes through capacitors C, and C,, past short circuit switchesSD, and SD, which likewise are operated by timer T. From there theconverted signal goes to buffer amplifiers BA, and BA, and emerge as theDC input to the synchro-to-digital converter described in the aforesaidSchroeder et al. US. Pat. No. 3,07l,324. The output of thesynchro-to-digital converter is then processed in a digital computer.

As shown in more detail in FIG. 4, the timer T may comprise in itspreferred form an input line 10 for receiving an AC reference inputsignal the frequency and phase of which is substantially equal to thatof each AC signal being sampled by switches S,S, and S,,-S,.,. This ACreference signal may be obtained from any convenient, well-known sourcesuch as an oscillator, for example. The input AC reference signal whichhas a waveform substantially as indicated by the letter A in FIG. 5, issimultaneously applied along a pair of branch lines 12 and 14 to a phaseshift network 16 and a zero-crossing detector 18. The output of phaseshift network 16 is also coupled to a zero-crossing detector 20, thelatter being substantially identical to detector 18. Phase shift network16 which comprises a conventional capacitor-resistor combinationproduces at its output a waveform which leads the waveform appearing online 14 at the input of zero-crossing detector 20 by an amountdetermined by the respective values of C,, and R,, as is well known inthe art. Thus, for example, assume again that the circuit of FIG. 3 hasbeen designed wherein from the table, wRC is equal to 1.6 and wt isequal to (l4l/l80)1r radians. Then the phase shift I of network 16 willbe equal to I- l4l or 39 of angular displacement in degrees electrical.

Zero-crossing detectors l8 and 20 which as explained above are exactlyidentical to one another are conventional logic components respectivelyadapted to provide a low or logical zero" output for all negative inputsand a high level or logical one output for all positive inputs.Therefore, taking into consideration the 39 phase lead of the signalinput to detector 18, the output waveforms of detectors l8 and 20 willappear as rectangular pulse trains represented respectively, bywaveforms B and C in FIG. 5. The rectangular pulse output ofzero-crossing detector 18 is applied to the input of NAND- gate 22 whilethe rectangular pulse output of zero-crossing detector 20 which lagsthat of zero-crossing detector 18 by 39 is applied simultaneously to theinput terminal of NAND-gate 24 and to the set input of flip-flop 28.Each of the NAND circuits employed in the present invention is of awell-known type which is responsive to a coincidence of positivepotentials or high-level logic "ones applied to its inputs to produce azero potential or low-level logical "zero at its output and is alsoresponsive to a zero potential applied to any one of its inputs toproduce a positive output potential. Thus, when the NAND gate has onlyone input as is the case with NAND-gates 22 and 24, it functions merelyas an inverter circuit. On the other hand NAND-gate 26 which has as itsinputs the respective outputs of inverters 22 and 24 functions as purelogical NAND as described above. The output of NAND-gate 26 issimultaneously applied to the reset input of flip-flop 28 and toswitches SD, and SD, of FIG. 3. Because of the inverter action ofNAND-gates 22 and 24, this output signal will be high or at the logicalone" level only when there is a lack of coincidence between thehigh-level logical one" portion of outputs B and C (FIG. 5) broughtabout the previously described 39 phase shift therebetween. Thus, theoutput of NAND-gate 26 may be represented by the pulse train D of FIG.5.

Flip-flop 28 is adapted to produce a high-level or logical one outputwhen a high-level or logical one" input is applied to its set input andto maintain this out-put until a highlevel or logical one" input isapplied to its reset input at which point the flip-flop will betriggeredtpraduse a low level or logical zero at its output until a subsequentlogical one" is once more applied to its set input. Thus, with referenceto FIG. 5, flip-flop 28 is triggered to its logical one" outputcondition by the leading edge of each pulse 30 in the output pulse trainC of zero-crossing detector and is reset to its logical zero" outputcondition by the leading edge of each alternate pulse 32 in the outputpulse train D of NAND-gate 26. The result is a pulse train output fromflipflop 28 having a waveform indicated at E in FIG. 5. Each of thepulses 34 in this output signal will be high or at the logical one levelfor a duration or pulse width equal to 141 electrical starting at thebeginning of each cycles of the input AC reference signal. Accordingly,each pulse 34 in the output signal E of flip-flop 28 may be adapted as atiming signal for applying the input signals sin A-sin D, and cos A-cosD across the respective RC networks of FIG. 3. Toward this end,

the output of the flip-flop 28 is commonly connected to a series of fourNAND-gates 36-42, each of which latter has its output coupled to a pairof corresponding switches for applying the correct synchro output acrossthe networks R,C, and R,,C,, of FIG. 3. Thus, for example, NAND-gate 36has its output connected to switches S, and S,, for actuation thereof toa closed condition, NAND-gate 38 has its output connected to switches Sand 8, and so on.

NAND-gates 36 through 42 also have a second input connected theretorespectively from an external address control or a multiplexing switchas shown (FIG. 4) whereby each pair of corresponding switches S,, S,,,8,, 8, etc. may be enable sequentially in a time-shared manner as iswell known in the art.

Thus, in the operation of the timer circuit of FIG. 4, assume that a 141pulse interval is beginning wherein the output of flip-flop 28 goes highas indicated at E in FIG. 5, and there simultaneously appears anenabling pulse along, say, the

secondary input line of NAND 36. In response, the NAND gate logicaloutput gate 36 will produce a zero" since both of its inputs are nowhigh or logical ones, which output will in turn, actuate switches S, andS,, to their closed condition. This, then, will cause the correspondingsin A and cos A input AC signals to be applied across the networks R,C,and R,,C,, for the interval of time determined by the width of pulse 34.The leading edge of pulse 32 will trigger or reset flip-flop 28 causingthe primary input to NAND-gate 36 to go to zero." The output of NAND 36will therefore also drop to zero" thereby opening switches S, and S,,.At the same time, the pulse 32 is being applied to switches SD, and SD:for actuating these switches to a closed condition and causing them toconnect the output of capacitors C, and C to ground thereby dischargingthe voltages on these capacitors which were built up during the previous141 interval. The next pulse 33 in the pulse train output of NAND-gate26 will then actuate switches SD, and SD, to their open-circuitedcondition to prepare the RC networks for the next sampling cycle which,of course, will begin by the closure of the next pair of switches S and8, in the same manner described above.

It is thus seen that the present invention contemplates a scheme forconverting an AC input to a DC output which latter is primarily afunction of the AC fundamental frequency with the input quadraturecomponents being entirely rejected and the input harmonics beingsubstantially attenuated. in its broadest form, the circuit of thepresent invention comprises.

line and its return path and a bufier amplifier fed by said line,

discharging its output into a DC output line. At a predeter- 'mineclangular position of the changing input sinusoidal volt age, a timer orsequencing means opens the switch in series with the input line so as tocut off the input to the circuit. This angularposition will bedetermined by the frequenc ofthe AC circuit and the values of thecapacitor and resistor. The optimum or desired output DC voltage withrespect to various values of resistors and capacitors for variousfrequencies can be calculated in the light of the mathematicalexpression for the transfer function of a sinusoidal value fed to an RCcircuit. In this way, values providing a high fundamental output, asmall output of harmonics, and zero quadrature voltages can be obtained.

What is claimed is:

l. in a circuit for the conversion of an AC input to a DC output whichis a function of the changing fundamental AC sinusoidal value, incombination,

a first AC input line and a return path;

said first AC input line having first and second junction points,

a first series switch in said first input line and disposed between saidjunction points;

a fist resistor in said first input line and in series with said firstswitch and disposed between said first and second junction points;

a second AC input line;

said second AC input line having a third junction;

a second series switch and a second resistor connected in series anddisposed between said third and second junction points;

a capacitor connected between said second junction point and said returnpath;

said resistors disposed respectively between said series switches andsaid capacitor;

a buffer amplifier fed by said resistors, discharging its out put into aDC output line; and

timer means adapted to open up said first and second series switches atpredetermined angular positions of the changing input sinusoidaldepending on the frequency of the AC circuit and the values of saidcapacitor and said first and second resistors, so as to obtain as aninput to the buffer amplifier a DC voltage having a large percentage ofthe AC sinusoidal fundamental component,

said buffer amplifier having a transfer function value, said transferfunction value of said buffer amplifier being such as to provide a DCoutput directly proportional to said AC fundamental input.

2. In a circuit as claimed in claim 1, including:

a third AC input line and a second return path;

a third series switch in said third input line and disposed between afourth and fifth junction points;

a third resistor in series with said third input line and said thirdseries switch and disposed between said fourth and fifth junctionpoints;

a fourth series switch and a fourth resistor connected in series betweena sixth junction point and said fifth junction point;

a second capacitor connected between said fifth junction point andsecond return path;

a second buffer amplifier fed by said third and fourth resistors,discharging its output into said AC output line, wherein said timermeans is adapted to selectively open said third and fourth seriesswitches at predetermined angular positions of the changing inputsinusoidal.

3. The circuit of claim 1 further comprising:

a short circuit switch in parallel with said capacitor and connectedbetween said second junction point and said return path effective todischarge the voltage on said capacitor when actuated to itsshort-circuited condition,

said timer means including means for actuating said switch to itsshorted circuited condition in response to said predetermined angularposition of the changing input sinusoidal.

1. In a circuit for the conversion of an AC input to a DC output whichis a function of the changing fundamental AC sinusoidal value, incombination, a first AC input line and a return path; said first ACinput line having first and second junction points, a first seriesswitch in said first input line and disposed between said junctionpoints; a fist resistor in said first input line and in series with saidfirst switch and disposed between said first and second junction points;a second AC input line; said second AC input line having a thirdjunction; a second series switch and a second resistor connected inseries and disposed between said third and second junction points; acapacitor connected between said second junction point and said returnpath; said resistors disposed respectively between said series switchesand said capacitor; a buffer amplifier fed by said resistors,discharging its output into a DC output line; and timer means adapted toopen up said first and second series switches at predetermined angularpositions of the changing input sinusoidal depending on the frequency ofthe AC circuit and the values of said capacitor and said first andsecond resistors, so as to obtain as an input to the buffer amplifier aDC voltage having a large percentage of the AC sinusoidal fundamentalcomponent, said buffer amplifier having a transfer function value, saidtransfer function value of said buffer amplifier being such as toprovide a DC output directly proportional to said AC fundamental input.2. In a circuit as claimed in claim 1, including: a third AC input lineand a second return path; a third series switch in said third input lineand disposed between a fourth and fifth junction points; a thirdresistor in series with said third input line and said third seriesswitch and disposed between said fourth and fifth junction points; afourth series switch and a fourth resistor connected in series between asixth junction point and said fifth junction point; a second capacitorconnected between said fifth junction point and second return path; asecond buffer amplifier fed by said third and fourth resistors,discharging its output into said DC output line, wherein said timermeans is adapted to selectively open said third and fourth seriesswitches at predetermined angular positions of the changing inputsinusoidal.
 3. The circuit of claim 1 further comprising: a shortcircuit switch in parallel with said capacitor and connected betweensaid second junction point and said return path effective to dischargethe voltage on said capacitor when actuated to its short-circuitedcondition, said timer means including means for actuating said switch toits shorted circuited condition in response to said predeterminedangular position of the changing input sinusoidal.